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cy7b9910 cy7b9920 low skew clock buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-07135 rev. *b revised august 07, 2007 features all outputs skew <100 ps typical (250 max.) 15 to 80 mhz output operation zero input to output delay 50% duty cycle outputs outputs drive 50 terminated lines low operating current 24-pin soic package jitter:<200 ps peak to peak, <25 ps rms functional description the cy7b9910 and cy7b9920 low skew clock buffers offer low skew system clock di stribution. these mu ltiple output clock drivers optimize the timing of high performance computer systems. each of the eight indi vidual drivers can drive terminated transmission lines with impedances as low as 50 . they deliver minimal and specified output skews and full swing logic levels (cy7b9910 ttl or cy7b9920 cmos). the completely integrated pll enables ?zero delay? capability. external divide capability, combined with the internal pll, allows distribution of a low frequency clo ck that is multiplied by virtually any factor at the clock destinatio n. this facility minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility. block diagram description phase frequency detector and filter the phase frequency de tector and filter blocks accept inputs from the reference frequency (ref) input and the feedback (fb) input and generate correction information to control the frequency of the voltage controlled oscillator (vco). these blocks, along with the vco, fo rm a phase locked loop (pll) that tracks the incoming ref signal. vco the vco accepts analog control i nputs from the pll filter block and generates a frequency. the oper ational range of the vco is determined by the fs control pin. test fb ref voltage controlled oscillator fs q0 filter phase freq det q1 q2 q3 q4 q5 q6 q7 logic block diagram [+] feedback
cy7b9910 cy7b9920 document number: 38-07135 rev. *b page 2 of 11 pin configuration test mode the test input is a three level input. in normal system operat ion, this pin is connected to ground, allowing the cy7b9910 and cy7b9920 to operate as described in block diagram description . for testing purposes, any of the three level inputs can have a removable jumper to ground or be tied low through a 100w resistor . this enables an external tester to change the state of these pins. if the test input is forced to its mid or high state, the device operates with its in ternal phase locked loop disconnected and input levels supplied to ref directly control all outputs. relative output-to-output functions are the same as in normal mode. pin definitions signal name io description ref i reference frequency input.this input supplies the frequency and timing against which all functional variations are measured. fb i pll feedback input (typically connec ted to one of the eight outputs). fs [1,2,3] i three level frequency range select. test i three level select. see test mode . q[0..7] o clock outputs. v ccn pwr power supply for output drivers. v ccq pwr power supply for in ternal circuitry. gnd pwr ground. q4 q2 ref v ccq fs nc v ccq v ccn q0 q1 gnd q3 v ccn gnd test nc gnd v ccn q7 q6 gnd q5 v ccn fb soic top view 1 2 3 4 5 6 7 8 9 10 11 12 15 16 17 18 19 20 24 23 22 21 13 14 7b9910 7b9920 notes 1. for all three state inputs, high indicates a connection to vcc, low indicates a connection to gnd, and mid indicates an open connection. internal termination circuitry holds an unconnected input to vcc/2. 2. the level to be set on fs is determined by the ?normal? operating frequency (fnom) of the vco (see logic block diagram ). the frequency appearing at the ref and fb inputs are fnom when the output connected to fb is undivided. the frequency of the ref and fb inputs are fnom/x when the device is configured for a frequency multiplication by using external division in the feedback path of value x. 3. when the fs pin is selected high, the ref input must not transition upon power up until vcc reached 4.3v. [+] feedback
cy7b9910 cy7b9920 document number: 38-07135 rev. *b page 3 of 11 maximum ratings operating outside these boundaries may affect the performance and life of the device. these user guidelines are not tested. storage temperature ................................. ?65 c to +150 c ambient temperature with power applied ............................................ ?55 c to +125 c supply voltage to ground potentia l................?0.5v to +7.0v dc input voltage ............................................?0.5v to +7.0v output current into outputs (low)............................. 64 ma static discharge voltage....... ........... ............ .............. >2001v (mil-std-883, method 3015) latch up current ..................................................... >200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10% industrial ?40 c to +85 c 5v 10% [+] feedback
cy7b9910 cy7b9920 document number: 38-07135 rev. *b page 4 of 11 electrical characteristics over the operating range cy7b9910 cy7b9920 parameter description test conditions min max min max unit v oh output high voltage v cc = min, i oh = ?16 ma 2.4 v v cc = min, i oh =?40 ma v cc ?0.75 v ol output low voltage v cc = min, i ol = 46 ma 0.45 v v cc = min, i ol = 46 ma 0.45 v ih input high voltage (ref and fb inputs only) 2.0 v cc v cc ? 1.35 v cc v v il input low voltage (ref and fb inputs only) ?0.5 0.8 ?0.5 1.35 v v ihh three level input high voltage (test, fs) [4] min v cc max v cc ? 1v v cc v cc ? 1v v cc v v imm three level input mid voltage (test, fs) [4] min v cc max v cc /2 ? 500 mv v cc /2 + 500 mv v cc /2 ? 500 mv v cc /2 + 500 mv v v ill three level input low voltage (test, fs) [4] min v cc max 0.0 1.0 0.0 1.0 v i ih input high leakage current (ref and fb inputs only) v cc = max, v in = max 10 10 a i il input low leakage current (ref and fb inputs only) v cc = max, v in = 0.4v ?500 ?500 a i ihh input high current (test, fs) v in = v cc 200 200 a i imm input mid current (test, fs) v in = v cc /2 ?50 50 ?50 50 a i ill input low current (test, fs) v in = gnd ?200 ?200 a i os output short circuit current [5] v cc = max, v out = gnd (25 c only) ?250 n/a ma i ccq operating current used by internal circuitry v ccn = v ccq = max all input selects open com?l 85 85 ma mil/ind 90 90 i ccn output buffer current per output pair [6] v ccn = v ccq = max i out = 0 ma input selects open, f max 14 19 ma pd power dissipation per output pair [7] v ccn = v ccq = max i out = 0 ma input selects open, f max 78 104 [5] mw notes 4. these inputs are normally wired to vcc, gnd, or left unconnected (actual threshold voltages vary as a percentage of vcc). int ernal termination resistors hold unconnected inputs at vcc/2. if these inputs are switched, the function and timing of the outputs may glitch and the pll may re quire an additional tlock time before all data sheet limits are achieved. 5. tested one output at a time, output shorted for less than one second, less than 10% duty cycle. room temperature only. cy7b99 20 outputs are not short circuit protected. 6. total output current per output pair is approximated by the fo llowing expression that includes device current plus load curre nt: cy7b9910: iccn = [(4 + 0.11f) + [((835 ? 3f)/z) + (.0022fc)]n] x 1.1 cy7b9920: iccn = [(3.5+.17f) + [((1160 ? 2.8f)/z) + (.0025fc)]n] x 1.1 where f = frequency in mhz c = capacitive load in pf z = line impedance in ohms n = number of loaded outputs; 0, 1, or 2 fc = f < c. 7. total power dissipation per output pair is approximated by th e following expression that includes device power dissipation pl us power dissipation due to the load circuit: cy7b9910: pd = [(22 + 0.61f) + [((1550 ? 2.7f)/z) + (.0125fc)]n] x 1.1 cy7b9920: pd = [(19.25+ 0.94f) + [((700 + 6f)/z) + (.017fc)]n] x 1.1.see note 3 for variable definition. [+] feedback
cy7b9910 cy7b9920 document number: 38-07135 rev. *b page 5 of 11 ac test loads and waveforms capacitance tested initially and after any design or proces s changes that may affect these parameters. parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 10 pf 7b9910?3 7b9910?4 ttl ac test load (cy7b9910) ttl input test waveform (cy7b9910) 5v r1 r2 c l r1 r2 c l 7b9910?5 cmos ac test load (cy7b9920) 3.0v 2.0v v th =1.5v 0.8v 0.0v 1ns 1ns 2.0v 0.8v v th =1.5v 80% v th =v cc /2 20% 0.0v 3ns 3ns 80% 20% v th =v cc /2 7b9910?6 cmos input test waveform (cy7b9920) v cc r1=130 r2=91 c l =50pf(c l = 30pf for ?5 and ? 2 devices) (includes fixture and probe capacitance) r1=100 r2=100 c l =50pf(c l =30 pf for ?5 and ? 2devices) (includes fixture and probe capacitance) v cc switching characteristics over the operating range [11] cy7b9910?2 [8] cy7b9920?2 [8] parameter description min typ max min typ max unit f nom operating clock frequency in mhz fs = low [1, 2] 15 30 15 30 mhz fs = mid [1, 2] 25 50 25 50 fs = high [1, 2, 3] 40 80 40 80 [12] t rpwh ref pulse width high 5.0 5.0 ns t rpwl ref pulse width low 5.0 5.0 ns t skew zero output skew (all outputs) [13, 14] 0.1 0.25 0.1 0.25 ns t dev device-to-device skew [14, 15] 0.75 0.75 ns t pd propagation delay, ref rise to fb rise ?0.25 0.0 +0.25 ?0.25 0.0 +0.25 ns t odcv output duty cycle variation [16] ?0.65 0.0 +0.65 ?0.65 0.0 +0.65 ns t orise output rise time [17, 18] 0.15 1.0 1.2 0.5 2.0 2.5 ns t ofall output fall time [17, 18] 0.15 1.0 1.2 0.5 2.0 2.5 ns t lock pll lock time [19] 0.5 0.5 ms t jr cycle-to-cycle output jitter peak to peak 200 200 ps rms 25 25 ps [+] feedback
cy7b9910 cy7b9920 document number: 38-07135 rev. *b page 6 of 11 cy7b9910?5 cy7b9920?5 parameter description min typ max min typ max unit f nom operating clock frequency in mhz fs = low [1, 2] 15 30 15 30 mhz fs = mid [1, 2] 25 50 25 50 fs = high [1, 2, 3] 40 80 40 80 [12] t rpwh ref pulse width high 5.0 5.0 ns t rpwl ref pulse width low 5.0 5.0 ns t skew zero output skew (all outputs) [13, 14] 0.25 0.5 0.25 0.5 ns t dev device-to-device skew [8, 15] 1.0 1.0 ns t pd propagation delay, ref rise to fb rise ?0.5 0.0 +0.5 ?0.5 0.0 +0.5 ns t odcv output duty cycle variation [16] ?1.0 0.0 +1.0 ?1.0 0.0 +1.0 ns t orise output rise time [17, 18 0.15 1.0 1.5 0.5 2.0 3.0 ns t ofall output fall time [17, 18] 0.15 1.0 1.5 0.5 2.0 3.0 ns t lock pll lock time [19] 0.5 0.5 ms t jr cycle-to-cycle output jitter peak to peak [8] 200 200 ps rms [8] 25 25 ps notes 8. guaranteed by statistical correlation. tested initially and af ter any design or process changes that may affect these paramet ers. 9. cmos output buffer current and power dissipation specified at 50 mhz reference frequency. 10. applies to ref and fb inputs only. 11. test measurement levels for the cy7b9910 are ttl levels (1.5v to 1.5v). test measurement levels for the cy7b9920 are cmos le vels (vcc/2 to vcc/2). test conditions assume signal transition times of 2ns or less and outp ut loading as shown in the ac test loads and waveforms unless otherwise specified. 12. except as noted, all cy7b9920?2 and ?5 timing para meters are specified to 80 mhz with a 30 pf load. 13. tskew is defined as the time between the earliest and the latest output transition among all outputs when all are loaded wit h 50 pf and terminated with 50 to 2.06v (cy7b9910) or vcc/2 (cy7b9920). 14. tskew is defined as the skew between outputs. 15. tdev is the output-to-output skew between any two outputs on separate devices operating under the same conditions (vcc, ambi ent temperature, air flow, and so on). 16. todcv is the deviation of the output from a 50% duty cycle. 17. specified with outputs loaded with 30 pf for the cy7b99x0?2 and ?5 devices and 50 pf for the cy7b99x0?7 devices. devices are terminated through 50 to 2.06v (cy7b9910) or vcc/2 (cy7b9920). 18. torise and tofall measured between 0.8v and 2.0v for the cy7b9910 or 0.8vcc and 0.2vcc for the cy7b9920. 19. tlock is the time that is required before synchronization is achieved. this specification is valid only after vcc is stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at ref or fb until tpd is within specified limits. [+] feedback
cy7b9910 cy7b9920 document number: 38-07135 rev. *b page 7 of 11 switching characteristics over the operating range [11] (continued) cy7b9910?7 cy7b9920?7 parameter description min typ max min typ max unit f nom operating clock frequency in mhz fs = low [1, 2] 15 30 15 30 mhz fs = mid [1, 2] 25 50 25 50 fs = high 1, 2, 3] 40 80 40 80 [12] t rpwh ref pulse width high 5.0 5.0 ns t rpwl ref pulse width low 5.0 5.0 ns t skew zero output skew (all outputs) [13, 14] 0.3 0.75 0.3 0.75 ns t dev device-to-device skew [8, 15] 1.5 1.5 ns t pd propagation delay, ref rise to fb rise ?0.7 0.0 +0.7 ?0.7 0.0 +0.7 ns t odcv output duty cycle variation [16] ?1.2 0.0 +1.2 ?1.2 0.0 +1.2 ns t orise output rise time [17, 18] 0.15 1.5 2.5 0.5 3.0 5.0 ns t ofall output fall time 17, 18] 0.15 1.5 2.5 0.5 3.0 5.0 ns t lock pll lock time [19] 0.5 0.5 ms t jr cycle-to-cycle output jitter peak to peak [8] 200 200 ps t jr rms [8] 25 25 ps [+] feedback
cy7b9910 cy7b9920 document number: 38-07135 rev. *b page 8 of 11 ac timing diagrams figure 1. ac timing diagrams figure 2. zero skew and zero delay clock driver t odcv t odcv t ref ref fb q other q t rpwh t rpwl t pd t skew t skew t jr system clock fb ref fs q0 q1 q2 q3 q4 q5 q6 q7 test z 0 load load load load ref z 0 z 0 z 0 [+] feedback
cy7b9910 cy7b9920 document number: 38-07135 rev. *b page 9 of 11 operational m ode descriptions figure 2 shows the device configured as a zero skew clock buffer. in this mode the 7b9910/9920 is used as the basis for a low skew clock distribution tree. the outputs are aligned and may each drive a terminated transmission line to an independent load. the fb input is tied to any output and the operating frequency range is selected with the fs pin. the low skew speci- fication, coupled with the ability to drive terminated transmission lines (with impedances as low as 50 ohms), enables efficient printed circuit board design. figure 1 shows the cy7b9910/9920 connected in series to construct a zero skew clock distribution tree between boards. cascaded clock buffers accu mulates low frequency jitter because of the non-ideal filtering characteristics of the pll filter. do not connect more than two clock buffers in series. figure 3. board-to-board clock distribution system clock z 0 fb ref fs test ref ref fs fb load load load load load test z 0 z 0 z 0 q0 q1 q2 q3 q4 q5 q6 q7 q0 q1 q2 q3 q4 q5 q6 q7 [+] feedback
cy7b9910 cy7b9920 document number: 38-07135 rev. *b page 10 of 11 ordering information accuracy (ps) ordering code package type operating range 250 cy7b9910?2sc 24-pb small outline ic commercial cy7b9910?2sct 24-pb small outline ic - tape and reel commercial cy7b9920?2sc [20] 24-pb small outline ic commercial 500 cy7b9910?5sc 24-pb small outline ic commercial cy7b9910?5sct 24-pb small outline ic - tape and reel commercial cy7b9910?5si 24-pb small outline ic industrial cy7b9910?5sit 24-pb small outline ic - tape and reel industrial cy7b9920?5sc 24-pb small outline ic commercial cy7b9920?5sct 24-pb small outline ic - tape and reel commercial cy7b9920?5si 24-pb small outline ic industrial 750 cy7b9910?7sc 24-pb small outline ic commercial cy7b9910?7si [20] 24-pb small outline ic industrial cy7b9920?7sc [20] 24-pb small outline ic commercial cy7b9920?7si [20] 24-pb small outline ic industrial pb-free 250 cy7b9910?2sxc 24-pb small outline ic commercial cy7b9910?2sxct 24-pb small outline ic - tape and reel commercial 500 cy7b9910?5sxc 24-pb small outline ic commercial cy7b9910?5sxct 24-pb small outline ic - tape and reel commercial cy7b9910?5sxi 24-pb small outline ic industrial cy7b9910?5sxit 24-pb small outline ic - tape and reel industrial 750 cy7b9910?7sxc 24-pb small outline ic commercial cy7b9910?7sxct 24-pb small outline ic - tape and reel commercial package diagram figure 4. 24-pin (300 mil) molded soic s13 51-85025-*c note 20. not recommended for new design. [+] feedback
document number: 38-07135 rev. *b revised august 07, 2007 page 11 of 11 psoc designer?, programmable system-on-chip ?, and psoc express? are trademarks and psoc? is a registered trademark of cypress s emiconductor corp. all other trademarks or registered trademarks referenced herein are property of the respective corporations. purchase of i 2 c components from cypress or one of its sublicense d associated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. all products and company names mentioned in this document may be the trademarks of their respective holders. cy7b9910 cy7b9920 ? cypress semiconductor corporation, 2001-2007.the information contained herein is subject to change without notice. cypress se miconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history document title: cy7b9910/cy7b9920 low skew clock buffer document number: 38-07135 rev. ecn no. issue date orig. of change description of change ** 110244 10/28/01 szv change from specif ication number: 38-00437 to 38-07135 *a 1199925 see ecn dpf/aesa added pb-free parts in ordering information added note 20: not recommended for the new design *b 1353343 see ecn aesa chang e status to final [+] feedback

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